DATA SHEET - The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a highperformance, packet-switched, interconnect technology.
Posted: May 31, 2004 | Published: April 1, 2004


Topics:  PCI Bus

DATA SHEET - SPI4P2 is a fully digital, multi-module design created to provide complete solution in variety of application scenarios: from dynamic alignment through protocol and FIFO management.
Posted: May 31, 2004 | Published: May 24, 2004


Topics:  PCI Bus

DATA SHEET - GPEX-RC is a highly flexible and configurable design targeted for root complex implementations in desktop, server and embedded applications.
Posted: May 31, 2004 | Published: May 24, 2004


Topics:  PCI Bus

DATA SHEET - GDA's HyperTransport Bridge core, code named HyperBridge, is designed for reuse and it's flexible backend interface makes it easy to be integrated into wide range of applications.
Posted: May 31, 2004 | Published: June 1, 2002


Topics:  Integrated Circuits | IP Core

DATA SHEET - GPEX-AS is a highly flexible and configurable end point controller IP targeted for both PCIExpress and Advanced Switching technology implementations in compute and communication applications.
Posted: May 31, 2004 | Published: January 1, 2004


Topics:  PCI Bus

DATA SHEET - GDA's XGEMAC is a highly configurable 10Gigabit Ethernet MAC core for use in multi gigabit chip designs. The core architecture is carefully tailored for high throughput, high performance, low latency and small silicon footprint.
Posted: May 31, 2004 | Published: August 1, 2003


Topics:  10 Gigabit Ethernet | IP Core

DATA SHEET - GDA's PCI Express interface controller is a highly flexible and configurable design targeted for end-point, root-complex, switch and bridge implementations in desktop, server, mobile, networking and telecom applications.
Posted: May 31, 2004 | Published: May 1, 2003


Topics:  PCI Bus

DATA SHEET - GDA's HyperTransport Host core, code named HyperHost, is designed for reuse and it's flexible backend interface makes it easy to be integrated into wide range of applications.
Posted: May 31, 2004 | Published: June 1, 2002


Topics:  Integrated Circuits | IP Core

DATA SHEET - GDA's HyperTransport Tunnel core, code named HyperTunnel, is designed for reuse and it's flexible backend interface makes it easy to be integrated into wide range of applications.
Posted: May 31, 2004 | Published: June 1, 2002


Topics:  Integrated Circuits | IP Core

DATA SHEET - GDA's HyperTransport Cave core, code named HyperCave, is designed for reuse and it's flexible backend interface makes it easy to be integrated into wide range of applications.
Posted: May 31, 2004 | Published: June 1, 2002


Topics:  Integrated Circuits | IP Core